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PowerPC Mnemonics
ムムムムムムムムムムムムムムムムム
Notes:
1. Instructions marked with a "*" are 64 bit instructions.
2. For description of operands, see notes at the end of this document.
3. For a fuller description of each instruction see PowerFantasms' documentation.
BRANCH PROCESSOR INSTRUCTIONS
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Note: Not all possible permutations of branch mnemonics are shown here as there
are 1024 possible combinations.
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Branch b target b,ba,bl,bla None
Branch conditional bc bo,bi,target bc,bca,bcl,bcla blt,ble,beq,bge
bgt,bnl,bne,bng
bso,bns,bun,bnu - eg. bne fred
Branch conditional bclr bo,bi,target bclr,bclrl As bc with lr appended
to link register
Branch conditional bcctr bo,bi,target bcctr,bcctrl As bc with ctr appended
to ctr register
System Call sc sc None
Condition register crand bt,ba,bb crand None
AND
Condition register cror bt,ba,bb cror crmove bx,by
OR
Condition register crxor crxor crclr bx
XOR
Condition register crnand bt,ba,bb crnand None
NAND
Condition register crnor bt,ba,bb crnor crnot bx,by
NOR
Condition register creqv bt,ba,bb creqv crset bx
equivalent
Condition register crandc bt,ba,bb crandc None
AND with complement
Condition register crorc bt,ba,bb crorc None
OR with complement
Move condition mcrf bf,bfa mcrf None
register field
FIXED POINT PROCESSOR INSTRUCTIONS
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
ムムムムムムムムムムFixed point load instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Load byte lbz rt,d(ra) lbz None
and zero
Load byte and lbzx rt,ra,rb lbzx None
zero indexed
Load byte and lbzu rt,d(ra) lbzu None
zero with update
Load byte and zero lbzux rt,ra,rb lbzux None
with update indexed
Load halfword lhz rt,d(ra) lhz None
and zero
Load halfword and lhzx rt,ra,rb lhzx None
zero indexed
Load halfword and lhzu rt,d(ra) lhzu None
zero with update
Load halfword and zero lhzux rt,ra,rb lhzux None
with update indexed
Load halfword lha rt,d(ra) lha None
algebraic
Load halfword lhax rt,ra,rb lhax None
algebraic indexed
Load halfword lhau rt,d(ra) lhau None
algebraic with update
Load halfword lhaux rt,ra,rb lhaux None
algebraic with update indexed
Load word and lwz rt,d(ra) lwz None
zero
Load word and lwzx rt,ra,rb lwzx None
zero indexed
Load word and lwzu rt,d(ra) lwzu None
zero with update
Load word and lwzux rt,ra,rb lwzux None
zero with update indexed
Load word lwa rt,ds(ra) lwa None
algebraic
Load word lwax rt,ra,rb lwax None
algebraic indexed
Load word algebraic lwaux rt,ra,rb lwaux None
with update indexed
Load doubleword* ld rt,ds(ra) ld None
Load doubleword ldx rt,ra,rb ldx None
indexed*
Load doubleword ldu rt,ds(ra) ldu None
with update*
Load doubleword ldux rt,ra,rb ldux None
with update indexed*
ムムムムムムムムムムFixed point store instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Store byte stb rs,d(ra) stb None
Store byte stbx rs,ra,rb stbx None
indexed
Store byte stbu rs,d(ra) stbu None
with update
Store byte stbux rs,ra,rb stbux None
with update indexed
Store halfword sth rs,d(ra) sth None
Store halfword sthx rs,ra,rb sthx None
indexed
Store halfword sthu rs,d(ra) sthu None
with update
Store halfword sthux rs,ra,rb sthux None
with update indexed
Store word stw rs,d(ra) stw None
Store word indexed stwx rs,ra,rb stwx None
Store word stwu rs,d(ra) stwu None
with update
Store word stwux rs,ra,rb stwux None
with update indexed
Store doubleword* std st,ds(ra) std None
Store doubleword stdx rs,ra,rb stdx None
indexed*
Store doubleword stdu rs,ds(ra) stdu None
with update*
Store doubleword stdux rs,ra,rb stdux None
with update indexed*
ムムムムムムムムムムFixed point load and store with byte reversal instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Load halfword byte lhbrx rt,ra,rb lhbrx None
reverse indexed
Load word byte lwbrx rt,ra,rb lwbrx None
reverse indexed
Store halfword byte sthbrx rs,ra,rb sthbrx None
reverse indexed
Store word byte stwbrx rs,ra,rb stwbrx None
reverse indexed
ムムムムムムムムムムFixed point load and store multiple instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Load multiple word lmw rt,d(ra) lmw None
Store multiple word stmw rs,d(ra) stmw None
ムムムムムムムムムムFixed point move assist instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Load string word lswi rt,ra,nb lswi None
immediate
Load string word lswx rt,ra,rb lswx None
indexed
Store string word stswi rs,ra,nb stswi None
immediate
Store string word stswx rs,ra,rb stswx None
indexed
ムムムムムムムムムStorage synchronisation functions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Load word and lwarx rt,ra,rb lwarx None
reserve indexed
Load doubleword and ldarx rt,ra,rb ldarx None
reserve indexed*
Store word conditional stwcx. rs,ra,rb stwcx. None
indexed
Store doubelword stdcx. rs,ra,rb stdcx. None
conditional indexed
Synchronise sync sync None
ムムムムムムムムムFixed point arithmetic
ムムムムムムムムムムムムムムムムムムムムムム
Add immediate addi rt,ra,si addi li rx,value - load immediate
la rx,disp(ry) - load address
subi rx,ry,value - subtract immediate
Add immediate shifted addis rt,ra,si addis lis rx,value - load immediate shifted
subis rx,ry,value - subtract immediate shifted
Add add rt,ra,rb add,add.,addo,addo. None
Subtract from subf rt,ra,rb subf,subf.,subfo sub rx,ry,rz
subfo.
Add immediate addic rt,ra,si addic,addic. subic[.] rx,ry,value
carrying
Subtract from subfic rt,ra,si subfic None
immediate carrying
Add carrying addc rt,ra,rb addc,addc.,addco None
addco.
Subtract from subfc rt,ra,rb subfc,subfc.,subfco subc rx,rz,ry
carrying subfco.
Add extended adde rt,ra,rb adde,adde.,addeo None
addeo.
Subtract from extended subfe rt,ra,rb subfe,subfe. None
subfeo,subfeo.
Add to minus 1 addme rt,ra addme,addme.,addmeo None
extended addmeo.
Subtract from minus subfme rt,ra subfme,subfme. None
1 extended subfmeo,subfmeo.
Add to zero extended addze rt,ra addze,addze. None
addzeo,addzeo.
Subtract from zero subfze rt,ra subfze,subfze. None
extended subfzeo,subfzeo.
Negate neg rt,ra neg,neg.,nego,nego. None
Multiply low mulli rt,ra,si mulli None
immediate
Mulitply low mulld rt,ra,rb mulld,mulld. None
doubleword* mulldo,mulldo.
Multiply low word mullw rt,ra,rb mullw,mullw. None
mullwo,mullwo.
Mulitply high mulhd rt,ra,rb mulhd,mulhd. None
doubleword*
Multiply high word mulhw rt,ra,rb mulhw,mulhw. None
Mulitply high mulhdu rt,ra,rb mulhdu,mulhdu. None
doubleword unsigned*
Multiply high word mulhwu rt,ra,rb mulhwu,mulhwu. None
unsigned
Divide doubleword* divd rt,ra,rb divd,divd. None
divdo,divdo.
Divide word divw rt,ra,rb divw,divw. None
divwo,divwo.
Divide doubleword divdu rt,ra,rb divdu,divdu. None
unsigned* divduo,divduo.
Divide word divwu rt,ra,rb divwu,divwu. None
unsigned divwuo,divwuo.
ムムムムムムムムムムムムFixed point compare instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Compare immediate cmpi bf,l,ra,si cmpi cmpwi rx,value - word compare result in cr0
cmpdi* cr2,rx,value - double word compare
Compare cmp bf,l,ra,rb cmp cmpw rx,ry - word compare result in cr0
cmpd* cr5,rx,ry - double word compare
Compare logical cmpli bf,l,ra,ui cmpli cmplwi rx,value - word compare result in cr0
immediate cmpldi* cr1,rx,value- double word compare result in cr1
Compare logical cmpl bf,l,ra,rb cmpl As cmpli
ムムムムムムムムムムムムTrap instructions
ムムムムムムムムムムムムムムムムム
Note: The trap instructions can take the same range of extended mnemonics are the branch
instructions - for example twgt, twlt etc
Trap doubleword* tdi to,ra,si tdi tdeqi
immediate
Trap word immediate twi to,ra,si twi twnei
Trap doubleword* td to,ra,rb td tdne rx,ry
Trap word tw to,ra,rb tw tweq rx,ry
ムムムムムムムムムムムFixed point logical instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
AND immediate andi. ra,rs,ui andi. None
AND immediate shifted andis. ra,rs,ui andis. None
OR immediate ori ra,rs,ui ori nop - no operation
OR immediate shifted oris ra,rs,ui oris None
XOR immediate xori ra,rs,ui xori None
XOR immediate shifted xoris ra,rs,ui xoris None
AND and ra,rs,rb and, and. None
OR or ra,rs,rb or,or. mr rx,ry - move register
XOR xor ra,rs,rb xor,xor. None
NAND nand ra,rs,rb nand,nand. None
NOR nor ra,rs,rb nor,nor. not rx,ry
Equivalent eqv ra,rs,rb eqv,eqv. None
AND with complement andc ra,rs,rb andc,andc. None
OR with complement orc ra,rs,rb orc,orc. None
Extend sign byte extsb ra,rs extsb,extsb. None
Extend sign halfword extsh ra,rs extsh,extsh. None
Extend sign word* extsw ra,rs extsw,extsw. None
Count leading zeros cntlzd ra,rs cntlzd,cntlzd. None
doubleword*
Count leading zeros cntlzw ra,rs cntlzw,cntlzw. None
word
ムムムムムムムムムムムムFixed point rotate and shift instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Note: Rotate and shift instructions can have up to five operands, thus Fantasm provides
all known 32 bit extended mnemonics as listed after the normal mnemonics.
Rotate left double rldicl ra,rs,sh,mb rldicl,rldicl. None
immediate then clear left*
Rotate left double rldicr ra,rs,sh,me rldicr,rldicr. None
immediate then clear right*
Rotate left double rldic ra,rs,sh,mb rldic,rldic. None
immediate then clear*
Rotate left word rlwinm ra,rs,sh,mb,me [.] See below
immediate then AND with mask
Rotate left double rldcl ra,rs,rb,mb rldcl,rldcl. None
then clear left*
Rotate left double rldcr ra,rs,rb,me rldcr,rldcr. None
then clear right*
Rotate left word rlwnm ra,rs,rb,mb,me [.] See below
then and with mask
Rotate left double rldimi ra,rs,sh,mb rldimi,rldimi. None
immediate then mask insert*
Rotate left word rlwimi ra,rs,sh,mb,me [.] See below
immediate then mask insert
Shift left double* sld ra,rs,rb sld,sld. None
Shift left word slw ra,rs,rb slw,slw. See below
Shift right double* srd ra,rs,rb srd,srd. None
Shift right word srw ra,rs,rb srw,srw. See below
Shift right algebraic sradi ra,rs,sh sradi,sradi. None
double immediate*
Shift right algebraic srawi ra,rs,sh srawi,srawi. See below
word immediate
Shift right algebraic srad ra,rs,sh srad,srad None
double*
Shift right algebraic sraw ra,rs,sh sraw,sraw. See below
word
Extended 32 bit shifts/rotates
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Note that In the following extended instructions:
Extract means: Select a field of n bits starting at bit position bin the source
register, right or left justify the field in the destination register and clear all the
other bits of the destination register to zeros.
Insert means: Select a left or right justified field of n bits in the source register,
and insert his field into the destination register at bit position b. Leave the other bits
of the destination register unchanged.
Rotate means: rotate the contents of a register right or left n bits.
Shift means: Shift the contents of the register right or left by n bits.
Clear means: Clear the leftmost or rightmost n bits of a register to zeros.
Clear left and shift left means: Clear the leftmost b bits of the register then
shift the register left by n bits.
Extract and left justify immediate extlwi ra,rs,n,b
Extract and right justify immediate extrwi ra,rs,n,b
Insert from left immediate inslwi ra,rs,n,b
Insert from right immediate insrwi ra,rs,n,b
Rotate left immediate rotlwi ra,rs,n
Rotate right immediate rotrwo ra,rs,n
Rotate left rotlw ra,rs,b
Shift left immediate slwi ra,rs,n
Shift right immediate srwi ra,rs,n
Clear left immediate clrlwi ra,rs,n
Clear right immediate clrrwi ra,rs,n
Clear left and shift immediate clrlslwi ra,rs,b,n
ムムムムムムムムムムムMove to/from system registers
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Move to Special mtspr SPR,rs mtspr mtxer,mtlr,mtctr
Purpose Register
Move from Special mfspr rs,SPR mfspr mfxer,mflr,mfctr
Purpose Register
Move to condition mtcrf fxm,rs mtcrf None
register fields
Move to condition mcrxr bf mcrxr None
register from XER
Move from condition mfcr rt mfcr None
register
PowerFantasm understands the following Special Purpose Registers (SPR's) - note the
definitions are in upper case only.
XER LR CTR
Priveledged SPRs:
DSISR DAR DEC SDR1 SRR0 SRR1 SPRG0 SPRG1 SPRG2 SPRG3 ASR EAR TBL TBU
PVR *read only
IBAT0U IBAT0L IBAT1U IBAT1L IBAT2U IBAT2L IBAT3U IBAT3L DBAT0U DBAT0L DBAT1U
DBAT1L DBAT2U DBAT2L DBAT3U DBAT3L
FLOATING POINT PROCESSOR
ムムムムムムムムムムムムムムムムムムムムムムムム
ムムムムムムムムムムFloating point load instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Load floating point lfs ft,d(ra) lfs None
single
Load floating point lfsx ft,ra,rb lfsx None
single indexed
Load floating point lfsu ft,d(ra) lfsu None
single with update
Load floating point lfsux ft,ra,rb lfsux None
single with update indexed
Load floating point lfd ft,d(ra) lfd None
double
Load floating point lfdx ft,ra,rb lfdx None
double indexed
Load floating point lfdu ft,d(ra) lfdu None
double with update
Load floating point lfdux ft,ra,rb lfsux None
double with update indexed
ムムムムムムムムムムFloating point store instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Store floating point stfs fs,d(ra) stfs None
single
Store floating point stfsx fs,ra,rb stfsx None
single indexed
Store floating point stfsu fs,d(ra) stfsu None
single with update
Store floating point stfsux fs,ra,rb stfsux None
single with update indexed
Store floating point stfd fs,d(ra) stfd None
double
Store floating point stfdx fs,ra,rb stfdx None
double indexed
Store floating point stfdu fs,d(ra) stfdu None
double with update
Store floating point stfdux fs,ra,rb stdsux None
double with update indexed
ムムムムムムムムムムFloating point move instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Floating move register fmr ft,fb fmr,fmr. None
Floating negate fneg ft,fb fneg,fneg. None
Floating absolute fabs ft,fb fabs,fabs. None
Floating negative fnabs ft,fb fnabs,fnabs. None
absolute
ムムムムムムムムムムFloating point arithmetic instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Floating add (single) fadd ft,fa,fb fadd, fadd. None
Floating subtract fsub ft,fa,fb fsub,fsub. None
(single)
Floating multiply fmul ft,fa,fb fmul,fmul. None
(single)
Floating divide fdiv ft,fa,fb fdiv,fdiv. None
(single)
Floating multiply-add fmadd ft,fa,fb,fc fmadd,fmadd. None
(single)
Floating multiply-sub fmsub ft,fa,fb,fc fmsub,fmsub. None
(single)
Floating negative fnmadd ft,fa,fb,fc fnmadd,fnmadd. None
multiply-add (single)
Floating negative fnmsub ft,fa,fb,fc fnmsub,fnmsub. None
multiply-subtract (single)
Floating round to frsp ft,fb frsp,frsp. None
single precision
Floating convert to fctid ft,fb fctid,fctid. None
doubleword*
Floating convert to fctidz ft,fb fctidz,fctidz. None
doubleword with round towards zero*
Floating convert to fctiw ft,fb fctiw,fctiw. None
integer word
Floating convert to fctiwz ft,fb fctiwz,fctiwz. None
integer word with round towards zero
Floating convert from fcfid ft,fb fcfid,fcfid. None
integer doubleword*
ムムムムムムムムムムFloating point compare instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Floating compare fcmpu bf,fa,fb fcmpu None
unordered
Floating compare fcmpo bf,fa,fb fcmpo None
ordered
ムムムムムムムムムムFloating point status and control register instructions
ムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムムム
Name Mnemonics Forms Extended
ムムムム ムムムムムムムムム ムムムムム ムムムムムムムム
Move from floating mffs ft mffs,mffs. None
point status and control register (FPSCR)
Move to condition mcrfs bf,bfa mcrfs None
register from FPSCR
Move to FPSCR field mtfsfi bf,u mtfsfi,mtfsfi. None
immediate
Move to FPSCR fields mtfsf flm,fb mtfsf,mtfsf. None
Move to fpscr bit 0 mtfsb0 bit mtfsb0,mtfdb0. None
Move the FPSCR bit 1 mtfsb1 bit mtfsb1,mtfsb1. None
ムムムムムムムムムムムムムムムムNOTES
ムムムムム
a and b are source operands when used with "f" or "r"
b is a bit.
ba and bb are bits used to specify a bit in the CR as a source.
bf is a bitfield used to specify a CR field as a target.
bfa is a bitfield used to specify a CR or FPSCR field as a source
bi is a field used to specify a bit in the CR.
bo is a field used to specify the options in a branch conditional instruction.
d 16 bit signed two's complement integer.
f is a floating point register
fa is an FPR (Floating Point Register) used as either source or destination.
fb is an FPR used as the source
flm is an 8 bit field mask.
fs is an FPR used as the source
ft is an FPR used as the target
l single bit field used to specify either 32 or 64 bit fixed point compares.
li 24 bit signed two's complement integer
mb is mask begin
me is mask end
nb is number of bytes to move
r is a general purpose register (GPR)
ra is a GPR used as either source or destination.
rb is a GPR used as the source
rs is a GPR used as the source
rt is a GPR used as the target
si is a 16 bit signed integer
t is target
to is a field used to specify the conditions under which a trap will be taken.
ui is an immediate unsigned 16 bit quantity
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